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A 47 , ˟, 10 Gb/s 1.4 mW/Gb/s Parallel Interface in 45 nm CMOS., , , , , , , , and . IEEE J. Solid State Circuits, 45 (12): 2828-2837 (2010)Guest Editorial Introduction to the Special Issue on the 2021 IEEE International Solid-State Circuits Conference (ISSCC)., and . IEEE J. Solid State Circuits, 56 (11): 3207-3208 (2021)Gm-boosted common-gate LNA and differential colpitts VCO/QVCO in 0.18-μm CMOS., , and . IEEE J. Solid State Circuits, 40 (12): 2609-2619 (2005)Improving Linearity in CMOS Phase Interpolators., , , and . IEEE J. Solid State Circuits, 58 (6): 1623-1635 (2023)Bandwidth Extension Techniques for CMOS Amplifiers., , and . IEEE J. Solid State Circuits, 41 (11): 2424-2439 (2006)A Dual-Polarization Silicon-Photonic Coherent Receiver Front-End Supporting 528 Gb/s/Wavelength., , , , , and . IEEE J. Solid State Circuits, 58 (8): 2202-2213 (2023)A Transformer-Based Technique to Improve Tuning Range and Phase Noise of a 20-28GHz LCVCO and a 51-62GHz Self-Mixing LCVCO., , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 69 (6): 2351-2363 (2022)A Case for Emerging Memories in DNN Accelerators., , , , and . DATE, page 938-941. IEEE, (2021)A Hilbert Transform Equalizer Enabling 80 MHz RF Self-Interference Cancellation for Full-Duplex Receivers., , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (3): 1153-1165 (2019)A 27Gb/s Forwarded-Clock I/O Receiver Using an Injection-Locked LC-DCO in 45nm CMOS., , , , , , , , and . ISSCC, page 452-453. IEEE, (2008)