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Auto-ViT-Acc: An FPGA-Aware Automatic Acceleration Framework for Vision Transformer with Mixed-Scheme Quantization.

, , , , , , , , , , , and . FPL, page 109-116. IEEE, (2022)

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Quick-Div: Rethinking Integer Divider Design for FPGA-based Soft-processors., , , and . ACM Trans. Reconfigurable Technol. Syst., 15 (3): 32:1-32:27 (2022)Demystifying the Soft and Hardened Memory Systems of Modern FPGAs for Software Programmers through Microbenchmarking., , and . ACM Trans. Reconfigurable Technol. Syst., 15 (4): 43:1-43:33 (2022)Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers through Microbenchmarking., , , and . FPGA, page 105-115. ACM, (2021)FPGA-aware automatic acceleration framework for vision transformer with mixed-scheme quantization: late breaking results., , , , , , , , , and 2 other author(s). DAC, page 1394-1395. ACM, (2022)Rethinking Integer Divider Design for FPGA-Based Soft-Processors., , , and . FCCM, page 289-297. IEEE, (2019)SASA: A Scalable and Automatic Stencil Acceleration Framework for Optimized Hybrid Spatial and Temporal Parallelism on HBM-based FPGAs., , , , , and . ACM Trans. Reconfigurable Technol. Syst., 16 (2): 28:1-28:33 (June 2023)ESRU: Extremely Low-Bit and Hardware-Efficient Stochastic Rounding Unit Design for Low-Bit DNN Training., , , , , , , , , and 2 other author(s). DATE, page 1-6. IEEE, (2023)Auto-ViT-Acc: An FPGA-Aware Automatic Acceleration Framework for Vision Transformer with Mixed-Scheme Quantization., , , , , , , , , and 2 other author(s). FPL, page 109-116. IEEE, (2022)You Already Have It: A Generator-Free Low-Precision DNN Training Framework Using Stochastic Rounding., , , , , , , , , and 4 other author(s). ECCV (12), volume 13672 of Lecture Notes in Computer Science, page 34-51. Springer, (2022)CHIP-KNN: A Configurable and High-Performance K-Nearest Neighbors Accelerator on Cloud FPGAs., , , and . FPT, page 139-147. IEEE, (2020)