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Auto-ViT-Acc: An FPGA-Aware Automatic Acceleration Framework for Vision Transformer with Mixed-Scheme Quantization.

Z. Li, M. Sun, A. Lu, H. Ma, G. Yuan, Y. Xie, H. Tang, Y. Li, M. Leeser, Z. Wang, X. Lin, and Z. Fang. FPL, page 109-116. IEEE, (2022)

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Yangpei Xie

Jian Xie

Qian Xie

Mingliang Xie

Zhenwei Xie

Other publications of authors with the same name

An Incremental Placement Flow for Advanced FPGAs With Timing Awareness.Z. Lin, Y. Xie, P. Zou, S. Wang, J. Yu, and J. Chen. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (9): 3092-3103 (2022)Invited: Algorithm-Software-Hardware Co-Design for Deep Learning Acceleration.Z. Li, Y. Xie, P. Dong, O. Chen, and Y. Wang. DAC, page 1-4. IEEE, (2023)TAAS: a timing-aware analytical strategy for AQFP-capable placement automation.P. Dong, Y. Xie, H. Li, M. Sun, O. Chen, N. Yoshikawa, and Y. Wang. DAC, page 1321-1326. ACM, (2022)FPGA-aware automatic acceleration framework for vision transformer with mixed-scheme quantization: late breaking results.M. Sun, Z. Li, A. Lu, H. Ma, G. Yuan, Y. Xie, H. Tang, Y. Li, M. Leeser, Z. Wang and 2 other author(s). DAC, page 1394-1395. ACM, (2022)Late Breaking Results: An Analytical Timing-Driven Placer for Heterogeneous FPGAs*.Z. Lin, Y. Xie, G. Qian, S. Wang, J. Yu, and J. Chen. DAC, page 1-2. IEEE, (2020)Machine Learning Across Network-Connected FPGAs.D. Diaconu, Y. Xie, M. Güngör, S. Handagala, X. Lin, and M. Leeser. HPEC, page 1-7. IEEE, (2023)Hardware-efficient stochastic rounding unit design for DNN training: late breaking results.S. Chang, G. Yuan, A. Lu, M. Sun, Y. Li, X. Ma, Z. Li, Y. Xie, M. Qin, X. Lin and 2 other author(s). DAC, page 1396-1397. ACM, (2022)A Life-Cycle Energy and Inventory Analysis of Adiabatic Quantum-Flux-Parametron Circuits.M. Zabihi, Y. Xie, Z. Li, P. Dong, G. Yuan, O. Chen, M. Pedram, and Y. Wang. CoRR, (2023)SupeRBNN: Randomized Binary Neural Network Using Adiabatic Superconductor Josephson Devices.Z. Li, G. Yuan, T. Yamauchi, M. Zabihi, Y. Xie, P. Dong, X. Tang, N. Yoshikawa, D. Tiwari, Y. Wang and 1 other author(s). MICRO, page 584-598. ACM, (2023)ESRU: Extremely Low-Bit and Hardware-Efficient Stochastic Rounding Unit Design for Low-Bit DNN Training.S. Chang, G. Yuan, A. Lu, M. Sun, Y. Li, X. Ma, Z. Li, Y. Xie, M. Qin, X. Lin and 2 other author(s). DATE, page 1-6. IEEE, (2023)

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Disambiguation of "Xie, Yanyue"

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Auto-ViT-Acc: An FPGA-Aware Automatic Acceleration Framework for Vision Transformer with Mixed-Scheme Quantization.

Please choose a person to relate this publication to

Yangpei Xie

Jian Xie

Qian Xie

Mingliang Xie

Zhenwei Xie

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Xie, Yanyue"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Auto-ViT-Acc: An FPGA-Aware Automatic Acceleration Framework for Vision Transformer with Mixed-Scheme Quantization.

Please choose a person to relate this publication to

Yangpei Xie

Jian Xie

Qian Xie

Mingliang Xie

Zhenwei Xie

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Auto-ViT-Acc: An FPGA-Aware Automatic Acceleration Framework for Vision Transformer with Mixed-Scheme Quantization.