( en | de | ru )

 

Disambiguation of "Shinohara, Hirofumi"

Author of the publication

copydeleteadd this publication to your clipboard
Highly Energy-Efficient SRAM With Hierarchical Bit Line Charge-Sharing Method Using Non-Selected Bit Line Charges.

, , , , , , and . IEEE J. Solid State Circuits, 48 (4): 924-931 (2013)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Kenichi Shinohara

Hirofumi Ishihara

Hirofumi Hosokawa

Hirofumi Kumazawa

Hirofumi Ueda

 

Other publications of authors with the same name

Post-silicon programmed body-biasing platform suppressing device variability in 45 nm CMOS technology., , , , , and . ISLPED, page 15-20. ACM, (2008)A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits., , , , , , , , , and 6 other author(s). IEEE J. Solid State Circuits, 42 (4): 820-829 (2007)A 64-bit carry look ahead adder using pass transistor BiCMOS gates., , , , and . IEEE J. Solid State Circuits, 31 (6): 810-818 (1996)A 0.116 pJ/bit Latch-Based True Random Number Generator Featuring Static Inverter Selection and Noise Enhancement., , , and . IEEE Trans. Very Large Scale Integr. Syst., 32 (3): 564-572 (March 2024)12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 voltage domains., , , , , and . ESSCIRC, page 191-194. IEEE, (2011)A 0.116pJ/bit Latch-Based True Random Number Generator with Static Inverter Selection and Noise Enhancement., , , , , and . VLSI-DAT, page 1-4. IEEE, (2022)Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability., , , , , , , , and . ICCAD, page 398-405. IEEE Computer Society, (2005)60% Cycle time acceleration, 55% energy reduction, 32Kbit SRAM by auto-selective boost (ASB) scheme for slow memory cells in random variations., , , , , and . ESSCIRC, page 317-320. IEEE, (2012)Accurate Nanopower Supply-Insensitive CMOS Unit Vth Extractor and αVth Extractor with Continuous Variety., , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 100-A (5): 1145-1155 (2017)A BiCMOS wired-OR logic., , , , and . IEEE J. Solid State Circuits, 30 (6): 622-628 (June 1995)