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Resource and data optimization for hardware implementation of deep neural networks targeting FPGA-based edge devices.

X. Liu, D. Kim, C. Wu, and D. Chen. SLIP@DAC, page 1:1-1:8. ACM, (2018)

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Liu Deming

Deming Sun

Deming Kong

Chen Chen

Other publications of authors with the same name

Performance-driven mapping for CPLD architectures.D. Chen, J. Cong, M. Ercegovac, and Z. Huang. FPGA, page 39-47. ACM, (2001)Debugging and verifying SoC designs through effective cross-layer hardware-software co-simulation.K. Campbell, L. He, L. Yang, S. Gurumani, K. Rupnow, and D. Chen. DAC, page 7:1-7:6. ACM, (2016)Optimality study of resource binding with multi-Vdds.D. Chen, J. Cong, Y. Fan, and J. Xu. DAC, page 580-585. ACM, (2006)Throughput-oriented kernel porting onto FPGAs.A. Papakonstantinou, D. Chen, W. mei W. Hwu, J. Cong, and Y. Liang. DAC, page 11:1-11:10. ACM, (2013)Resource and data optimization for hardware implementation of deep neural networks targeting FPGA-based edge devices.X. Liu, D. Kim, C. Wu, and D. Chen. SLIP@DAC, page 1:1-1:8. ACM, (2018)Analytical SPICE-Compatible Model of Schottky-Barrier-Type GNRFETs With Performance Analysis.M. Gholipour, Y. Chen, A. Sangai, N. Masoumi, and D. Chen. IEEE Trans. Very Large Scale Integr. Syst., 24 (2): 650-663 (2016)Introduction.D. Chen. ACM Trans. Reconfigurable Technol. Syst., 9 (4): 28:1-28:2 (2016)ScaleHLS: A New Scalable High-Level Synthesis Framework on Multi-Level Intermediate Representation.H. Ye, C. Hao, J. Cheng, H. Jeong, J. Huang, S. Neuendorffer, and D. Chen. HPCA, page 741-755. IEEE, (2022)High-level synthesis with behavioral level multi-cycle path analysis.H. Zheng, S. Gurumani, L. Yang, D. Chen, and K. Rupnow. FPL, page 1-8. IEEE, (2013)Behavioral-level IP integration in high-level synthesis.L. Yang, S. Gurumani, D. Chen, and K. Rupnow. FPT, page 172-175. IEEE, (2015)

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Disambiguation of "Chen, Deming"

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Resource and data optimization for hardware implementation of deep neural networks targeting FPGA-based edge devices.

Please choose a person to relate this publication to

Liu Deming

Deming Sun

Deming Kong

Deming Kong

Chen Chen

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Chen, Deming"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Resource and data optimization for hardware implementation of deep neural networks targeting FPGA-based edge devices.

Please choose a person to relate this publication to

Liu Deming

Deming Sun

Deming Kong

Deming Kong

Chen Chen

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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Resource and data optimization for hardware implementation of deep neural networks targeting FPGA-based edge devices.