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Disambiguation of "Fasoli, Andrea"

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4-Bit Quantization of LSTM-Based Speech Recognition Models.

, , , , , , , , , , , and . Interspeech, page 2586-2590. ISCA, (2021)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Hemma Fasoli

Diego Fasoli

Daniela Fasoli-Wörmann

Andrea Witzenrath

Risikofaktoren für abdominelle Komplikationen nach kardiopulmonalem Bypass. Uni Erlangen-Nürnberg, (2009)

Andrea Rottach

Analysis of the cell cycle dependent dynamics of Dnmt1 and Np95 in living cells. Uni München, (2009)
 

Other publications of authors with the same name

Toward Software-Equivalent Accuracy on Transformer-Based Deep Neural Networks With Analog Memory Devices., , , , , , , , , and 1 other author(s). Frontiers Comput. Neurosci., (2021)Phase Change Memory-based Hardware Accelerators for Deep Neural Networks (invited)., , , , , , , , , and 15 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)4-Bit Quantization of LSTM-Based Speech Recognition Models., , , , , , , , , and 2 other author(s). Interspeech, page 2586-2590. ISCA, (2021)An analog-AI chip for energy-efficient speech recognition and transcription., , , , , , , , , and 14 other author(s). Nat., 620 (7975): 768-775 (2023)Neuromorphic Computing with Phase Change, Device Reliability, and Variability Challenges., , , , , , , , , and . IRPS, page 1-10. IEEE, (2020)Hardware-aware training for large-scale and diverse deep learning inference workloads using in-memory computing-based accelerators., , , , , , , , , and 3 other author(s). CoRR, (2023)Sputtering of Metal Oxide Semiconductor n-p Stacks., , , , and . ISOEN, page 1-3. IEEE, (2019)Accelerating Inference and Language Model Fusion of Recurrent Neural Network Transducers via End-to-End 4-bit Quantization., , , , , , , and . INTERSPEECH, page 2038-2042. ISCA, (2022)Accelerating Deep Neural Networks with Analog Memory Devices., , , , , , , , and . AICAS, page 149-152. IEEE, (2020)Architectures and Circuits for Analog-memory-based Hardware Accelerators for Deep Neural Networks (Invited)., , , , , , , , , and 13 other author(s). ISCAS, page 1-5. IEEE, (2023)