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Disambiguation of "Kaliorakis, Manolis"

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MeRLiN: Exploiting Dynamic Instruction Behavior for Fast and Accurate Microarchitecture Level Reliability Assessment.

, , , and . ISCA, page 241-254. ACM, (2017)

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Manolis Skarsoulis

Manolis Kamvysselis

Konstantin Manolis

Manolis Fanto

Manolis Pasparakis

 

Other publications of authors with the same name

Bayesian network early reliability evaluation analysis for both permanent and transient faults., , , , , , , and . IOLTS, page 7-12. IEEE, (2015)A Digital Twin for Maritime Situational Awareness., , , , , , , and . BDCAT, page 26:1-26:2. ACM, (2023)Measuring and Exploiting Guardbands of Server-Grade ARMv8 CPU Cores and DRAMs., , , , , , , , , and 2 other author(s). DSN Workshops, page 6-9. IEEE Computer Society, (2018)Microprocessor reliability-performance tradeoffs assessment at the microarchitecture level., , , , and . VTS, page 1-6. IEEE Computer Society, (2016)Micro-Viruses for Fast System-Level Voltage Margins Characterization in Multicore CPUs., , , , and . ISPASS, page 54-63. IEEE Computer Society, (2018)A Scalable System for Maritime Route and Event Forecasting., , , , , , , , , and 2 other author(s). EDBT, page 762-769. OpenProceedings.org, (2024)GMSA: A Digital Twin Application for Maritime Route and Event Forecasting., , , , , , , , , and 2 other author(s). EDBT, page 798-801. OpenProceedings.org, (2024)An energy-efficient and error-resilient server ecosystem exceeding conservative scaling limits., , , , , , , , , and 16 other author(s). DATE, page 1099-1104. IEEE, (2018)RT Level vs. Microarchitecture-Level Reliability Assessment: Case Study on ARM(R) Cortex(R)-A9 CPU., , , , , , and . DSN Workshops, page 117-120. IEEE Computer Society, (2017)Accelerated online error detection in many-core microprocessor architectures., , , and . VTS, page 1-6. IEEE Computer Society, (2014)