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Disambiguation of "Najafi, Ardalan"

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Coherent Design of Hybrid Approximate Adders: Unified Design Framework and Metrics

, , , and . IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 8 (4): 736-745 (2018)
DOI: http://dx.doi.org/10.1109/JETCAS.2018.2833284

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Faraz Najafi

Hossein Najafi

Ardalan Zargham

Abdolsamad Ardalan

Mahshid Najafi

 

Other publications of authors with the same name

Coherent Design of Hybrid Approximate Adders: Unified Design Framework and Metrics, , , and . IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 8 (4): 736-745 (2018)Systematic Design of an Approximate Adder: The Optimized Lower Part Constant-OR Adder., , and . IEEE Trans. Very Large Scale Integr. Syst., 26 (8): 1595-1599 (2018)CNN Sensor Analytics With Hybrid-Float6 Quantization on Low-Power Embedded FPGAs., , , , , , , and . IEEE Access, (2023)Coherent Design of Hybrid Approximate Adders: Unified Design Framework and Metrics., , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 8 (4): 736-745 (2018)Exploiting Neural-Network Statistics for Low-Power DNN Inference., , and . CoRR, (2023)On the Effects of Data Distribution on Small-error Approximate Adders., , and . MOCAST, page 1-4. IEEE, (2020)High-speed energy-efficient 5: 2 compressor., , and . MIPRO, page 80-84. IEEE, (2014)FLINT+: A Runtime-Configurable Emulation-Based Stochastic Timing Analysis Framework, , , , , and . International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), IEEE, (2017)A Fair Comparison of Adders in Stochastic Regime, , , and . International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), IEEE, (2017)Stochastic Wave-Pipelined On-Chip Interconnect., , and . IEEE Trans. Circuits Syst. II Express Briefs, 67-II (5): 841-845 (2020)