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Disambiguation of "Deka, Jatindra Kumar"

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Abstractions for model checking of event timings.

, , , and . ISCAS (5), page 125-128. IEEE, (2001)

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Jürgen Deka

Wolfgang Dekant

Hans-Joachim Dekan

Adolf Dekant

Anja Dekant

 

Other publications of authors with the same name

On-Line Analysis of Stuck-at Faults in On-Chip Network Interconnects., , and . Journal of Circuits, Systems, and Computers, 27 (13): 1850203:1-1850203:13 (2018)A Low-Cost Test Solution for Reliable Communication in Networks-on-Chip., , , and . J. Electron. Test., 35 (2): 215-243 (2019)Retesting Defective Circuits to Allow Acceptable Faults for Yield Enhancement., , and . J. Electron. Test., 37 (5): 633-652 (2021)Incomplete Testing of SOC., , and . J. Electron. Test., 39 (3): 387-402 (June 2023)Reliability Monitoring in a Smart NoC Component., , and . ICECS, page 1-4. IEEE, (2020)Systematic Design of Approximate Adder Using Significance Based Gate-Level Pruning (SGLP) for Image Processing Application., , and . PReMI (2), volume 11942 of Lecture Notes in Computer Science, page 561-570. Springer, (2019)Directed Symbolic Execution for VLSI Circuits., , and . SMC, page 50-55. IEEE, (2015)One poison is antidote against another poison., , , and . SMC, page 4579-4584. IEEE, (2016)A packet address driven test strategy for stuck-at faults in networks-on-chip interconnects., , and . MED, page 176-183. IEEE, (2015)Reliability-Aware Test Methodology for Detecting Short-Channel Faults in On-Chip Networks., , , and . IEEE Trans. Very Large Scale Integr. Syst., 26 (6): 1026-1039 (2018)