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Disambiguation of "Takahashi, Yasuo"

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Experimental and Simulation Studies of Single-Electron-Transistor-Based Multiple-Valued Logic.

, and . ISMVL, page 259-266. IEEE Computer Society, (2003)

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Teruaki Takahashi

Yasuo Kamata

Yasuo Tokunaga

Yasuo Nakayama

Kotaro Takahashi

 

Other publications of authors with the same name

Design of a Two-Bit-Per-Cell Content-Addressable Memory Using Single-Electron Transistors., , , , and . J. Multiple Valued Log. Soft Comput., 13 (3): 249-266 (2007)Transfer and Detection of Single Electrons Using Metal-Oxide-Semiconductor Field-Effect Transistors., , , , , , , and . IEICE Trans. Electron., 90-C (5): 943-948 (2007)A Two-Bit-per-Cell Content-Addressable Memory Using Single-Electron Transistors., , , , and . ISMVL, page 32-38. IEEE Computer Society, (2005)Effect of Arrangement of Input Gates on Logic Switching Characteristics of Nanodot Array Device., , , , , , , and . IEICE Trans. Electron., 95-C (5): 865-870 (2012)Anomalous microstructure formed at the interface between copper ribbon and tin-deposited copper plate by ultrasonic bonding., , , , and . Microelectron. Reliab., 51 (1): 130-136 (2011)Brownian Circuits: Designs., , , , , , , , , and . Int. J. Unconv. Comput., 12 (5-6): 341-362 (2016)Associative search using pseudo-analog memristors., , , , , , , and . ISCAS, page 1-4. IEEE, (2017)A Single-Electron-Transistor Logic Gate Family and Its Application - Part II: Design and Simulation of a 7-3 Parallel Counter with Linear Summation and Multiple-Valued Latch Functions., , , , and . ISMVL, page 269-274. IEEE Computer Society, (2004)Experimental and Simulation Studies of Single-Electron-Transistor-Based Multiple-Valued Logic., and . ISMVL, page 259-266. IEEE Computer Society, (2003)Full Adder Operation Based on Si Nanodot Array Device with Multiple Inputs and Outputs., , , , , , , and . Int. J. Nanotechnol. Mol. Comput., 1 (2): 58-69 (2009)