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Disambiguation of "Borkar, Nitin"

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Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor.

, , , , , , , , , , , and . ISSCC, page 174-175. IEEE, (2010)

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Milind Borkar

Sirin Nitinawarat

Nitin Nangare

Nitin Suresh

Sachin Borkar

 

Other publications of authors with the same name

System-Level Power Analysis of a Multicore Multipower Domain Processor With ON-Chip Voltage Regulators., , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (12): 3468-3476 (2016)An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS., , , , , , , , , and 4 other author(s). ISSCC, page 98-589. IEEE, (2007)A 2 Tb/s 6 , ˟, 4 Mesh Network for a Single-Chip Cloud Computer With DVFS in 45 nm CMOS., , , , , , , , and . IEEE J. Solid State Circuits, 46 (4): 757-766 (2011)Design Challenges in Sub-100nm High Performance Microprocessors., , , and . VLSI Design, page 15-17. IEEE Computer Society, (2004)Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 46 (1): 184-193 (2011)A 4.2GHz 0.3mm2 256kb Dual-Vcc SRAM Building Block in 65nm CMOS., , , , , , , , , and 3 other author(s). ISSCC, page 2572-2581. IEEE, (2006)A 90mW/GFlop 3.4GHz Reconfigurable Fused/Continuous Multiply-Accumulator for Floating-Point and Integer Operands in 65nm., , , , , , and . VLSI Design, page 252-257. IEEE Computer Society, (2010)Resiliency for many-core system on a chip., , , , , , and . ASP-DAC, page 388-389. IEEE, (2014)A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS., , , , , , , , , and 11 other author(s). ISSCC, page 66-68. IEEE, (2012)An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS., , , , , , , , , and 5 other author(s). IEEE J. Solid State Circuits, 43 (1): 29-41 (2008)