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Disambiguation of "Howard, Jason"

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Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor.

, , , , , , , , , , , and . ISSCC, page 174-175. IEEE, (2010)

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Ian Jason

Howard Nelson

Howard Foster

Howard Li

Jason Miskuly

 

Other publications of authors with the same name

Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 46 (1): 184-193 (2011)A 4.2GHz 0.3mm2 256kb Dual-Vcc SRAM Building Block in 65nm CMOS., , , , , , , , , and 3 other author(s). ISSCC, page 2572-2581. IEEE, (2006)The Intel Programmable and Integrated Unified Memory Architecture Graph Analytics Processor., , , , , , , , , and 10 other author(s). IEEE Micro, 43 (5): 78-87 (September 2023)The First Direct Mesh-to-Mesh Photonic Fabric.. HCS, page 1-17. IEEE, (2023)A 256-Kb Dual-VCC SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 42 (1): 233-242 (2007)A TCP offload accelerator for 10 Gb/s Ethernet in 90-nm CMOS., , , , , , , , , and 5 other author(s). IEEE J. Solid State Circuits, 38 (11): 1866-1875 (2003)PIUMA: Programmable Integrated Unified Memory Architecture., , , , , , , , , and 21 other author(s). CoRR, (2020)An IA-32 processor with a wide voltage operating range in 32nm CMOS., , , , , , , , , and 9 other author(s). Hot Chips Symposium, page 1-37. IEEE, (2012)2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process., , , , , , , , , and 1 other author(s). ISSCC, page 274-275. IEEE, (2008)Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor., , , , , , , , , and 2 other author(s). ISSCC, page 174-175. IEEE, (2010)