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Disambiguation of "Shibata, Hajime"

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Adaptive digital noise-cancellation filtering using cross-correlators for continuous-time MASH ADC in 28nm CMOS.

, , , , , , , , , and . CICC, page 1-4. IEEE, (2017)

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Hajime Sakai

Daisuke Shibata

Tomohiro Shibata

Hajime Konno

Hajime Myoken

 

Other publications of authors with the same name

Frequency Response Analysis of Latch Utilized in High-Speed Comparator., , , and . ICECS, page 1077-1080. IEEE, (2006)A LTE RX front-end with digitally programmable multi-band blocker cancellation in 28nm CMOS., , , and . CICC, page 1-4. IEEE, (2017)A DC-to-1 GHz Tunable RF Delta Sigma ADC Achieving DR = 74 dB and BW = 150 MHz at f0 = 450 MHz Using 550 mW., , , , , , , and . IEEE J. Solid State Circuits, 47 (12): 2888-2897 (2012)A 6.4-GS/s 1-GHz BW Continuous-Time Pipelined ADC with Time-Interleaved Sub-ADC-DAC Achieving 61.7-dB SNDR in 16-nm FinFET., , , , , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)A 1-MHz-Bandwidth Continuous-Time Delta-Sigma ADC Achieving >90dB SFDR and >80dB Antialiasing Using Reference-Switched Resistive Feedback DACs., , , , , , , , , and 1 other author(s). CICC, page 1-2. IEEE, (2023)Automated Design of Analog Circuits Using Cell-Based Structure ., , and . Evolvable Hardware, page 85-92. IEEE Computer Society, (2002)Analog circuit synthesis by superimposing of sub-circuits., and . ISCAS (5), page 427-430. IEEE, (2001)Continuous-Time Pipelined Analog-to-Digital Converters: A Mini-Tutorial., and . IEEE Trans. Circuits Syst. II Express Briefs, 68 (3): 810-815 (2021)Advances in high-speed continuous-time delta-sigma modulators., , , , and . CICC, page 1-8. IEEE, (2014)A 6.4-GS/s 1-GHz BW Continuous-Time Pipelined ADC With Time-Interleaved Sub-ADC-DAC Achieving 61.7-dB SNDR in 16-nm FinFET., , , , , , , and . IEEE J. Solid State Circuits, 59 (4): 1158-1170 (April 2024)