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A New Scan Power Reduction Scheme Using Transition Freezing for Pseudo-Random Logic BIST.

, , , , and . IEICE Trans. Inf. Syst., 91-D (4): 1185-1188 (2008)

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A Novel Massively Parallel Testing Method Using Multi-Root for High Reliability., , and . IEEE Trans. Reliab., 64 (1): 486-496 (2015)Path search engine for fast optimal path search using efficient hardware architecture., , , and . ISOCC, page 96-99. IEEE, (2011)Broadcast scan compression based on deterministic pattern generation algorithm., , , and . ISQED, page 449-453. IEEE, (2017)Test data reduction method based on berlekamp-massey algorithm., , , and . ISOCC, page 123-124. IEEE, (2017)Route Reinforcement for Efficient QoS Routing Based on Ant Algorithm., , , and . ICOIN, volume 3090 of Lecture Notes in Computer Science, page 342-349. Springer, (2004)A Practical Test Scheduling Using Network-Based TAM in Network on Chip Architecture., , and . Asia-Pacific Computer Systems Architecture Conference, volume 3740 of Lecture Notes in Computer Science, page 614-624. Springer, (2005)A Memory-Efficient Pattern Matching with Hardware-Based Bit-Split String Matchers for Deep Packet Inspection., , , , and . IEICE Trans. Commun., 93-B (2): 396-398 (2010)A Secure Scan Architecture Protecting Scan Test and Scan Dump Using Skew-Based Lock and Key., , and . IEEE Access, (2021)Reconfigurable Scan Architecture for High Diagnostic Resolution., , and . IEEE Access, (2021)Enhanced Postbond Test Architecture for Bridge Defects Between the TSVs., , and . IEEE Trans. Very Large Scale Integr. Syst., 29 (6): 1164-1177 (2021)