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Aggressor aware repeater circuits for improving on-chip bus performance and robustness.

, , and . ESSCIRC, page 261-264. IEEE, (2003)

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Technology exploration for adaptive power and frequency scaling in 90nm CMOS., , and . ISLPED, page 14-19. ACM, (2004)Reducing Cross-Talk Induced Power Consumption and Delay., , and . PATMOS, volume 3254 of Lecture Notes in Computer Science, page 179-188. Springer, (2004)Body bias driven design synthesis for optimum performance per area., and . ISQED, page 472-477. IEEE, (2010)CMDS: Cross-layer Dataflow Optimization for DNN Accelerators Exploiting Multi-bank Memories., , , , , , and . ISQED, page 1-8. IEEE, (2023)Analysis of the Influence of Substrate on the Performance of On-Chip MOS Decoupling Capacitors., and . IEEE J. Solid State Circuits, 44 (2): 484-494 (2009)An Activity Monitor for Power/Performance Tuning of CMOS Digital Circuits., , and . PATMOS, volume 3728 of Lecture Notes in Computer Science, page 187-196. Springer, (2005)Active Noise Cancellation Using Aggressor-Aware Clamping Circuit for Robust On-Chip Communication., , and . VLSI Design, page 325-329. IEEE Computer Society, (2005)CMDS: Cross-layer Dataflow Optimization for DNN Accelerators Exploiting Multi-bank Memories., , , , , , and . CoRR, (2024)A forward body bias generator for digital CMOS circuits with supply voltage scaling., , , , , , and . ISCAS, page 2482-2485. IEEE, (2010)Glitch-free discretely programmable clock generation on chip., , and . ISCAS (2), page 1839-1842. IEEE, (2005)