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A CAD Open Platform for High Performance Reconfigurable Systems in the EXTRA Project.

, , , , , , , , and . ISVLSI, page 368-373. IEEE Computer Society, (2017)

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A CAD Open Platform for High Performance Reconfigurable Systems in the EXTRA Project., , , , , , , , and . ISVLSI, page 368-373. IEEE Computer Society, (2017)A Framework with Cloud Integration for CNN Acceleration on FPGA Devices., , , and . IPDPS Workshops, page 170-177. IEEE Computer Society, (2018)A Pipelined and Scalable Dataflow Implementation of Convolutional Neural Networks on FPGA., , , and . IPDPS Workshops, page 90-97. IEEE Computer Society, (2017)Optimizing streaming stencil time-step designs via FPGA floorplanning., , , , and . FPL, page 1-4. IEEE, (2017)A Feedback-Based Design Space Exploration Subsystem for the Automation of Architectures Synthesis on Proprietary FPGA Toolchains., , and . DSD, page 151-154. IEEE Computer Society, (2017)Enabling transparent hardware acceleration on Zynq SoC for scientific computing., , , , , and . SIGBED Rev., 17 (1): 30-35 (2020)On How to Accelerate Iterative Stencil Loops: A Scalable Streaming-Based Approach., , , , and . ACM Trans. Archit. Code Optim., 12 (4): 53:1-53:26 (2016)On How to Design Dataflow FPGA-Based Accelerators for Convolutional Neural Networks., , and . ISVLSI, page 639-644. IEEE Computer Society, (2017)An FPGA-Based Acceleration Methodology and Performance Model for Iterative Stencils., , , and . IPDPS Workshops, page 115-122. IEEE Computer Society, (2018)Heterogeneous exascale supercomputing: The role of CAD in the exaFPGA project., , , , , and . DATE, page 410-415. IEEE, (2017)