Author of the publication

15.1 A 0.795fJ/bit Physically-Unclonable Function-Protected TCAM for a Software-Defined Networking Switch.

, , , , , , , and . ISSCC, page 276-278. IEEE, (2024)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A Multi-Modal Face Recognition Method Using Complete Local Derivative Patterns and Depth Maps., , , , and . Sensors, 14 (10): 19561-19581 (2014)Aggressive Pipelining of Irregular Applications on Reconfigurable Hardware., , , , , and . ISCA, page 575-586. ACM, (2017)LCP: a layer clusters paralleling mapping method for accelerating inception and residual networks on FPGA., , , , , and . DAC, page 16:1-16:6. ACM, (2018)An efficient kernel transformation architecture for binary- and ternary-weight neural network inference., , , , and . DAC, page 137:1-137:6. ACM, (2018)A 2.69 Mbps/mW 1.09 Mbps/kGE Conjugate Gradient-based MMSE Detector for 64-QAM 128×8 Massive MIMO Systems., , , , , and . A-SSCC, page 191-194. IEEE, (2018)Polyhedral model based mapping optimization of loop nests for CGRAs., , , and . DAC, page 19:1-19:8. ACM, (2013)Data cache prefetching via context directed pattern matching for coarse-grained reconfigurable arrays., , , and . DAC, page 64:1-64:6. ACM, (2016)Energy-aware loops mapping on multi-vdd CGRAs without performance degradation., , , and . ASP-DAC, page 312-317. IEEE, (2017)Hybrid circuit-switched network for on-chip communication in large-scale chip-multiprocessors., , , and . J. Parallel Distributed Comput., 74 (9): 2818-2830 (2014)Hierarchical representation of on-chip context to reduce reconfiguration time and implementation area for coarse-grained reconfigurable architecture., , , , , , and . Sci. China Inf. Sci., 56 (11): 1-20 (2013)