Author of the publication

A digital hardware implementation of spiking neural networks with binary FORCE training.

, , and . Neurocomputing, (2020)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Reliability-Aware Task Scheduling using Clustered Replication for Multi-core Real-Time systems., , , , and . NoCArc@MICRO, page 45-50. ACM, (2016)Reliability aware throughput management of chip multi-processor architecture via thread migration., , , and . J. Supercomput., 72 (4): 1363-1380 (2016)A Novel Merged Multiplier-Accumulator Embedded in DSP Coprocessor., , and . ICECS, page 119-122. IEEE, (2006)Design of NBTI-resilient extensible processors., , , and . Integr., (2015)An efficient temperature dependent hot carrier injection reliability simulation flow., , , , and . Microelectron. Reliab., (2016)Implementation-aware selection of the custom instruction set for extensible processors., , , , , and . Microprocess. Microsystems, 38 (7): 681-691 (2014)A reconfigurable real-time neuromorphic hardware for spiking winner-take-all network., and . Int. J. Circuit Theory Appl., 48 (12): 2141-2152 (2020)Fast Parallel Model Estimation on the Cell Broadband Engine., , , , and . ISVC (2), volume 6454 of Lecture Notes in Computer Science, page 469-480. Springer, (2010)Inherent reliability evaluation of Networks-on-Chip based on analytical models., , and . SoC, page 1-4. IEEE, (2008)Negative Exponential Distribution Traffic Pattern for Power/Performance Analysis of Network on Chips., , , , and . VLSI Design, page 157-162. IEEE Computer Society, (2009)