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Negative Exponential Distribution Traffic Pattern for Power/Performance Analysis of Network on Chips.

, , , , and . VLSI Design, page 157-162. IEEE Computer Society, (2009)

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An Efficient Temporal Data Prefetcher for L1 Caches., , and . IEEE Comput. Archit. Lett., 16 (2): 99-102 (2017)EDXY - A low cost congestion-aware routing algorithm for network-on-chips., , , , and . J. Syst. Archit., 56 (7): 256-264 (2010)TED+: a data structure for microprocessor verification., , , , and . ASP-DAC, page 567-572. ACM Press, (2005)AxBench: A Benchmark Suite for Approximate Computing Across the System Stack, , , and . (2016)ORIGAMI: A Heterogeneous Split Architecture for In-Memory Acceleration of Learning., , , and . CoRR, (2018)Scale-Out Processors & Energy Efficiency., , , , and . CoRR, (2018)Die-Stacked DRAM: Memory, Cache, or MemCache?, , , and . CoRR, (2018)Optimizing Data-Center TCO with Scale-Out Processors., , , , , and . IEEE Micro, 32 (5): 52-63 (2012)Chapter Three - Temporal prefetching., and . Adv. Comput., (2022)Enhanced TED: A New Data Structure for RTL Verification., , , and . VLSI Design, page 481-486. IEEE Computer Society, (2008)