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Technology/Memory Co-Design and Co-Optimization Using E-Tree Interconnect.

Z. Pei, M. Mayahinia, H. Liu, M. Tahoori, F. Catthoor, Z. Tokei, and C. Pan. ACM Great Lakes Symposium on VLSI, page 159-162. ACM, (2023)

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Zsolt Szücs

Zsolt Szabó

Zsolt Zrinyi

Zsolt Szentiványi

Zsolt Szabó

Other publications of authors with the same name

A tool flow for predicting system level timing failures due to interconnect reliability degradation.J. Guo, A. Papanikolaou, M. Stucchi, K. Croes, Z. Tokei, and F. Catthoor. ACM Great Lakes Symposium on VLSI, page 291-296. ACM, (2008)Layout dependency induced deviation from Poisson area scaling in BEOL dielectric reliability.Y. Li, Z. Tökei, P. Roussel, G. Groeseneken, and K. Maex. Microelectron. Reliab., 45 (9-11): 1299-1304 (2005)First demonstration of Two Metal Level Semi-damascene Interconnects with Fully Self-aligned Vias at 18MP.G. Murdoch, M. O'Toole, G. Marti, A. Pokhrel, D. Tsvetanova, S. Decoster, S. Kundu, Y. Oniki, A. Thiam, Q. Le and 5 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2022)Low-Frequency Noise Measurements to Characterize Cu-Electromigration Down to 44nm Metal Pitch.S. Beyne, O. Pedreira, I. Wolf, Z. Tökei, and K. Croes. IRPS, page 1-6. IEEE, (2019)Stress mitigation of 3D-stacking/packaging induced stresses.K. Croes, V. Cherman, M. Lofrano, H. Zahedmanesh, L. Kljucar, M. Gonzalez, I. Wolf, Z. Tökei, and E. Beyne. IRPS, page 4. IEEE, (2018)Metal reliability mechanisms in Ruthenium interconnects.O. Pedreira, M. Stucchi, A. Gupta, V. Vega-Gonzalez, M. van der Veen, S. Lariviere, C. Wilson, Z. Tökei, and K. Croes. IRPS, page 1-7. IEEE, (2020)Global Is the New Local: FPGA Architecture at 5nm and Beyond.S. Nikolic, F. Catthoor, Z. Tokei, and P. Ienne. FPGA, page 34-44. ACM, (2021)As-grown donor-like traps in low-k dielectrics and their impact on intrinsic TDDB reliability.B. Tang, K. Croes, Y. Barbarin, Y. Wang, R. Degraeve, Y. Li, M. Toledano-Luque, T. Kauerauf, J. Bömmels, Z. Tökei and 1 other author(s). Microelectron. Reliab., 54 (9-10): 1675-1679 (2014)Electromigration limits of copper nano-interconnects.H. Zahedmanesh, O. Pedreira, Z. Tokei, and K. Croes. IRPS, page 1-6. IEEE, (2021)Reliability of a DME Ru Semidamascene scheme with 16 nm wide Airgaps.A. Lesniewska, O. Pedreira, M. Lofrano, G. Murdoch, M. van der Veen, A. Dangol, N. Horiguchi, Z. Tökei, and K. Croes. IRPS, page 1-6. IEEE, (2021)

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Disambiguation of "Tokei, Zsolt"

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URL
DOI
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Chicago
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Technology/Memory Co-Design and Co-Optimization Using E-Tree Interconnect.

Please choose a person to relate this publication to

Zsolt Szücs

Zsolt Szabó

Zsolt Zrinyi

Zsolt Szentiványi

Zsolt Szabó

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Tokei, Zsolt"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Technology/Memory Co-Design and Co-Optimization Using E-Tree Interconnect.

Please choose a person to relate this publication to

Zsolt Szücs

Zsolt Szabó

Zsolt Zrinyi

Zsolt Szentiványi

Zsolt Szabó

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Technology/Memory Co-Design and Co-Optimization Using E-Tree Interconnect.