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Disambiguation of "Zeng, Xuan"

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TS-SHES: Terrain Segmentation in Complex-Valued PolSAR Images Via Scattering Harmonization and Explicit Supervision.

, , , , and . IEEE Trans. Geosci. Remote. Sens., (2022)

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Haibo Xuan

Zhengrong Xuan

Yue Xuan

Chaoting Xuan

Yimin Xuan

 

Other publications of authors with the same name

SemiPSCN: Polarization Semantic Constraint Network for Semi-Supervised Segmentation in Large-Scale and Complex-Valued PolSAR Images., , , , , , and . IEEE Trans. Geosci. Remote. Sens., (2024)DENet: Double-Encoder Network With Feature Refinement and Region Adaption for Terrain Segmentation in PolSAR Images., , , , and . IEEE Trans. Geosci. Remote. Sens., (2022)DPFF-Net: Dual-Polarization Image Feature Fusion Network for SAR Ship Detection., , , , , , and . IEEE Trans. Geosci. Remote. Sens., (2023)RingMo-Lite: A Remote Sensing Lightweight Network With CNN-Transformer Hybrid Framework., , , , , , , , , and 2 other author(s). IEEE Trans. Geosci. Remote. Sens., (2024)Efficient Statistical Timing Analysis for Circuits with Post-Silicon Tunable Buffers., , , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 97-A (11): 2227-2235 (2014)BBGP-sDFO: Batch Bayesian and Gaussian Process Enhanced Subspace Derivative Free Optimization for High-Dimensional Analog Circuit Synthesis., , , , , , , , , and 3 other author(s). IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 43 (2): 417-430 (February 2024)Efficient Layout Hotspot Detection via Binarized Residual Neural Network Ensemble., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40 (7): 1476-1488 (2021)Binning Optimization for Transparently-Latched Circuits., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 30 (2): 270-283 (2011)GNN-Cap: Chip-Scale Interconnect Capacitance Extraction Using Graph Neural Network., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 43 (4): 1206-1217 (April 2024)Efficient Approximation Algorithms for Chemical Mechanical Polishing Dummy Fill., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 30 (3): 402-415 (2011)