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Clock-aware ultrascale FPGA placement with machine learning routability prediction: (Invited paper).

C. Pui, G. Chen, Y. Ma, E. Young, and B. Yu. ICCAD, page 929-936. IEEE, (2017)

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Beatrice Puiu

Ale PuÌ

Wa Longmei

Heinz Puin

David Puig Jordán

Other publications of authors with the same name

Lagrangian Relaxation-Based Time-Division Multiplexing Optimization for Multi-FPGA Systems.C. Pui, and E. Young. ICCAD, page 1-8. ACM, (2019)CUGR: Detailed-Routability-Driven 3D Global Routing with Probabilistic Resource Model.J. Liu, C. Pui, F. Wang, and E. Young. DAC, page 1-6. IEEE, (2020)Simultaneous Reconnection Surgery Technique of Routing With Machine Learning-Based Acceleration.P. Tu, C. Pui, and E. Young. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (6): 1245-1257 (2020)Heterogeneous Graph Neural Network-Based Imitation Learning for Gate Sizing Acceleration.X. Zhou, J. Ye, C. Pui, K. Shao, G. Zhang, B. Wang, J. Hao, G. Chen, and P. Heng. ICCAD, page 57:1-57:9. ACM, (2022)Legalization algorithm for multiple-row height standard cell design.W. Chow, C. Pui, and E. Young. DAC, page 83:1-83:6. ACM, (2016)Multi-FPGA Co-optimization: Hybrid Routing and Competitive-based Time Division Multiplexing Assignment.D. Zheng, X. Zhang, C. Pui, and E. Young. ASP-DAC, page 176-182. ACM, (2021)Device Layer-Aware Analytical Placement for Analog Circuits.B. Xu, S. Li, C. Pui, D. Liu, L. Shen, Y. Lin, N. Sun, and D. Pan. ISPD, page 19-26. ACM, (2019)RippleFPGA: a routability-driven placement for large-scale heterogeneous FPGAs.C. Pui, G. Chen, W. Chow, K. Lam, J. Kuang, P. Tu, H. Zhang, E. Young, and B. Yu. ICCAD, page 67. ACM, (2016)Dr. CU: Detailed Routing by Sparse Grid Graph and Minimum-Area-Captured Path Search.G. Chen, C. Pui, H. Li, and E. Young. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (9): 1902-1915 (2020)Lagrangian Relaxation-Based Time-Division Multiplexing Optimization for Multi-FPGA Systems.C. Pui, and E. Young. ACM Trans. Design Autom. Electr. Syst., 25 (2): 21:1-21:23 (2020)

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Disambiguation of "Pui, Chak-Wa"

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Clock-aware ultrascale FPGA placement with machine learning routability prediction: (Invited paper).

Please choose a person to relate this publication to

Beatrice Puiu

Ale PuÌ

Wa Longmei

Heinz Puin

David Puig Jordán

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Pui, Chak-Wa"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Clock-aware ultrascale FPGA placement with machine learning routability prediction: (Invited paper).

Please choose a person to relate this publication to

Beatrice Puiu

Ale PuÌ

Wa Longmei

Heinz Puin

David Puig Jordán

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Clock-aware ultrascale FPGA placement with machine learning routability prediction: (Invited paper).