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Disambiguation of "Johann, Marcelo O."

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Unbalacing the I/O Pins Partitioning for Minimizing Inter-Tier Vias in 3D VLSI Circuits.

, , , and . ICECS, page 399-402. IEEE, (2006)

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Marcelo Ephraim

Marcelo Trallero

Marcelo Giovannetti

Marcelo Klötzle

Marcelo Bertasso

 

Other publications of authors with the same name

Effective Method for Simultaneous Gate Sizing and $V$ th Assignment Using Lagrangian Relaxation., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 33 (4): 546-557 (2014)A Method for I/O Pins Partitioning Targeting 3D VLSI Circuits., , , and . VLSI-SoC (Selected Papers), volume 249 of IFIP, page 259-279. Springer, (2006)Rsyn: An Extensible Physical Synthesis Framework., , , , and . ISPD, page 33-40. ACM, (2017)A Mesh-Buffer Displacement Optimization Strategy., , , and . ISVLSI, page 282-287. IEEE Computer Society, (2010)A polyphonic pitch tracking embedded system for rapid instrument augmentation., , , and . NIME, page 120-125. nime.org, (2018)Ecologically grounded multimodal design: The Palafito 1.0 study., , , , , , , , and . ICMC, Michigan Publishing, (2014)An Incremental Timing-Driven flow using quadratic formulation for detailed placement., , , , , , and . VLSI-SoC, page 1-6. IEEE, (2015)Interaction Aesthetics and Ubiquitous Music., , , , , , and . Creativity in the Digital Age, Springer, (2015)Maze routing steiner trees with effective critical sink optimization., , , and . ISPD, page 135-142. ACM, (2007)Fast and efficient lagrangian relaxation-based discrete gate sizing., , , and . DATE, page 1855-1860. EDA Consortium San Jose, CA, USA / ACM DL, (2013)