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Disambiguation of "Rzepa, Gerhard"

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Co-integration Process Compatible Input/Output (I/O) Device Options for GAA Nanosheet Technology.

, , , , , , , , and . ESSDERC, page 265-268. IEEE, (2022)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Gerhard Schröck

Risk management and value creation in financial institutions. Uni Augsburg, (2001)

Johannes Gerhard

Normal vectors for the robust design of dynamical systems. TU Aachen, (2010)

Gerhard Jakob Schmitt-Gerhard

Gerhard Siebert

Gerhard Schulte

 

Other publications of authors with the same name

Accelerated Capture and Emission (ACE) Measurement Pattern for Efficient BTI Characterization and Modeling., , , , , , , , , and . IRPS, page 1-7. IEEE, (2019)Quantum Mechanical Charge Trap Modeling to Explain BTI at Cryogenic Temperatures., , , , , , , , and . IRPS, page 1-6. IEEE, (2020)Characterization and physical modeling of the temporal evolution of near-interfacial states resulting from NBTI/PBTI stress in nMOS/pMOS transistors., , , , , , , , , and 1 other author(s). IRPS, page 2. IEEE, (2018)Comphy - A compact-physics framework for unified modeling of BTI., , , , , , , , , and 4 other author(s). Microelectron. Reliab., (2018)A TCAD Compatible SONOS Trapping Layer Model for Accurate Programming Dynamics., , , , , , , , and . IMW, page 1-4. IEEE, (2021)Characterization and modeling of charge trapping: From single defects to devices., , , , , , , , and . ICICDT, page 1-4. IEEE, (2014)Physical modeling of the hysteresis in M0S2 transistors., , , , , , , , , and . ESSDERC, page 284-287. IEEE, (2017)The Mysterious Bipolar Bias Temperature Stress from the Perspective of Gate-Sided Hydrogen Release., , , , , and . IRPS, page 1-6. IEEE, (2020)Co-integration Process Compatible Input/Output (I/O) Device Options for GAA Nanosheet Technology., , , , , , , , and . ESSDERC, page 265-268. IEEE, (2022)Gate-Stack Engineered NBTI Improvements in Highvoltage Logic-For-Memory High-ĸ/Metal Gate Devices., , , , , , , , , and 6 other author(s). IRPS, page 1-8. IEEE, (2019)