( en | de | ru )

 

Disambiguation of "Litta, E. Dentoni"

Author of the publication

copydeleteadd this publication to your clipboard
Gate-Stack Engineered NBTI Improvements in Highvoltage Logic-For-Memory High-ĸ/Metal Gate Devices.

, , , , , , , , , , , , , , , and . IRPS, page 1-8. IEEE, (2019)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Henriette Litta

Thore Litta

Heinz Littaur

Charlotte Littauer

Emil Littann

 

Other publications of authors with the same name

Gate-Stack Engineered NBTI Improvements in Highvoltage Logic-For-Memory High-ĸ/Metal Gate Devices., , , , , , , , , and 6 other author(s). IRPS, page 1-8. IEEE, (2019)Demonstration of 3D sequential FD-SOI on CMOS FinFET stacking featuring low temperature Si layer transfer and top tier device fabrication with tier interconnections., , , , , , , , , and 15 other author(s). VLSI Technology and Circuits, page 330-331. IEEE, (2022)Bias Temperature Instability (BTI) of High-Voltage Devices for Memory Periphery., , , , , , , , , and 7 other author(s). IRPS, page 1-6. IEEE, (2022)Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails., , , , , , , , , and 34 other author(s). VLSI Technology and Circuits, page 284-285. IEEE, (2022)Novel low thermal budget gate stack solutions for BTI reliability in future Logic Device technologies : Invited paper., , , , , , , , , and 3 other author(s). ICICDT, page 1-4. IEEE, (2021)Novel Low Thermal Budget CMOS RMG: Performance and Reliability Benchmark Against Conventional High Thermal Budget Gate Stack Solutions., , , , , , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)Integration of a Stacked Contact MOL for Monolithic CFET., , , , , , , , , and 13 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning., , , , , , , , , and 30 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)Molybdenum Nitride as a Scalable and Thermally Stable pWFM for CFET., , , , , , , , , and 11 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)High Performance Thermally Resistant FinFETs DRAM Peripheral CMOS FinFETs with VTH Tunability for Future Memories., , , , , , , , , and 12 other author(s). VLSI Technology and Circuits, page 306-307. IEEE, (2022)