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Synthesis of reversible logic circuits.

, , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 22 (6): 710-722 (2003)

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Matthew John Hayes

John P Burrows

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John P Teschke

 

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Node fault tolerance in graphs., и . Networks, 27 (1): 19-23 (1996)On Realizations of Boolean Functions Requiring a Minimal or Near-Minimal Number of Tests.. IEEE Trans. Computers, 20 (12): 1506-1513 (1971)Detection of Pattern-Sensitive Faults in Random-Access Memories.. IEEE Trans. Computers, 24 (2): 150-157 (1975)A Fault-Tolerant Communication Scheme for Hypercube Computers., и . IEEE Trans. Computers, 41 (10): 1242-1256 (1992)Some Practical Issues in the Design of Fault-Tolerant Multiprocessors., и . IEEE Trans. Computers, 41 (5): 588-598 (1992)Testing Memories for Single-Cell Pattern-Sensitive Faults.. IEEE Trans. Computers, 29 (3): 249-254 (1980)Test Point Placement to Simplify Fault Detection., и . IEEE Trans. Computers, 23 (7): 727-735 (1974)Edge fault tolerance in graphs., и . Networks, 23 (2): 135-142 (1993)Scalar-Vector Memory Interference in Vector Computers., и . ICPP (1), стр. 180-187. CRC Press, (1991)Architecture of a Hypercube Supercomputer., , и . ICPP, стр. 653-660. IEEE Computer Society Press, (1986)