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Disambiguation of "Hayes, John P."

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Synthesis of reversible logic circuits.

, , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 22 (6): 710-722 (2003)

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Matthew John Hayes

John P Burrows

John P Brown

John P Broussard

John P Teschke

 

Other publications of authors with the same name

Edge fault tolerance in graphs., and . Networks, 23 (2): 135-142 (1993)General Modeling and Technology-Mapping Technique for LUT-Based FPGAs., and . FPGA, page 43-49. ACM, (1997)On the Functions Realized by Stochastic Computing Circuits., and . ACM Great Lakes Symposium on VLSI, page 331-336. ACM, (2015)Framework for quantifying and managing accuracy in stochastic circuit design., , and . DATE, page 1-6. IEEE, (2017)A 3.6mW 2.4-GHz multi-channel super-regenerative receiver in 130nm CMOS., , and . CICC, page 361-364. IEEE, (2005)Scalable Test Generators for High-Speed Datapath Circuits., , and . J. Electron. Test., 12 (1-2): 111-125 (1998)A Fully Integrated Auto-Calibrated Super-Regenerative Receiver in 0.13-µm CMOS., , and . IEEE J. Solid State Circuits, 42 (9): 1976-1985 (2007)Realization-independent ATPG for designs with unimplemented blocks., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 20 (2): 290-306 (2001)The Promise and Challenge of Stochastic Computing., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (8): 1515-1531 (2018)Designing for high-level test generation., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 9 (7): 752-766 (1990)