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Disambiguation of "Joseph, Russ"

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Exploration of associative power management with instruction governed operation for ultra-low power design.

, , , and . DAC, page 152:1-152:6. ACM, (2016)

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Erich Ruß

Bernhard Russ

Detlev Russ

Walter Russ

Walter Russ

 

Other publications of authors with the same name

Spatially- and temporally-adaptive communication protocols for zero-maintenance sensor networks relying on opportunistic energy scavenging., , and . CODES+ISSS, page 235-244. ACM, (2012)Process variation characterization of chip-level multiprocessors., , , , and . DAC, page 694-697. ACM, (2009)Power deregulation: eliminating off-chip voltage regulation circuitry from embedded systems., , and . CODES+ISSS, page 105-110. ACM, (2007)Exploring circuit timing-aware language and compilation., , and . ASPLOS, page 345-356. ACM, (2011)Exploration of associative power management with instruction governed operation for ultra-low power design., , , and . DAC, page 152:1-152:6. ACM, (2016)Enabling Deep Voltage Scaling in Delay Sensitive L1 Caches., and . DSN, page 192-202. IEEE Computer Society, (2016)D2M: data-driven model for fast and accurate timing error simulation in statically scheduled microprocessors., and . SummerSim, page 4:1-4:13. Society for Computer Simulation International / ACM DL, (2017)Virtual-machine-based emulation of future generation high-performance computing systems., , , , , , , and . Int. J. High Perform. Comput. Appl., 26 (2): 125-135 (2012)Three-Dimensional Chip-Multiprocessor Run-Time Thermal Management., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (8): 1479-1492 (2008)An Adaptive Clock Scheme Exploiting Instruction-Based Dynamic Timing Slack for a GPGPU Architecture., , , and . IEEE J. Solid State Circuits, 55 (8): 2259-2269 (2020)