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Capacitance and Yield Evaluations Using a 90-nm Process Technology Based on the Dense Power-Ground Interconnect Architecture.

A. Kurokawa, M. Yamamoto, N. Ono, T. Kage, Y. Inoue, and H. Masuda. ISQED, page 153-158. IEEE Computer Society, (2005)

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Yasuaki Saigusa

Heide Inoue

Tomoyuki Inoue

Hiroko Inoue

Norman Inoue

Other publications of authors with the same name

Formula-Based Method for Capacitance Extraction of Interconnects with Dummy Fills.A. Kurokawa, A. Kasebe, T. Kanamoto, Y. Yang, Z. Huang, Y. Inoue, and H. Masuda. IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 89-A (4): 847-855 (2006)Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew.Z. Huang, A. Kurokawa, J. Pan, and Y. Inoue. IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 88-A (12): 3367-3374 (2005)A Novel Model for Computing the Effective Capacitance of CMOS Gates with Interconnect Loads.Z. Huang, A. Kurokawa, Y. Inoue, and J. Mao. IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 88-A (10): 2562-2569 (2005)A 3.5ppm/°C 0.85V Bandgap Reference Circuit without Resistors.J. Wang, Q. Li, L. Ding, H. Shinohara, and Y. Inoue. IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 99-A (7): 1430-1437 (2016)Accurate Method for Calculating the Effective Capacitance with RC Loads Based on the Thevenin Model.M. Jiang, Z. Huang, A. Kurokawa, S. Fang, and Y. Inoue. IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 92-A (10): 2531-2539 (2009)A Highly Linear and Wide Input Range Four-Quadrant CMOS Analog Multiplier Using Active Feedback.Z. Huang, M. Jiang, and Y. Inoue. IEICE Trans. Electron., 92-C (6): 806-814 (2009)Efficient Large Scale Integration Power/Ground Network Optimization Based on Grid Genetic Algorithm.Y. Yang, A. Kurokawa, Y. Inoue, and W. Zhao. IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 88-A (12): 3412-3420 (2005)A Low-Power Sub-1-V Low-Voltage Reference Using Body Effect.J. Pan, Y. Inoue, Z. Liang, Z. Huang, and W. Huang. IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 90-A (4): 748-755 (2007)A low voltage CMOS rectifier for wirelessly powered devices.Q. Li, R. Zhang, Z. Huang, and Y. Inoue. ISCAS, page 873-876. IEEE, (2010)A CMOS Sub-l-V nanopower current and voltage reference with leakage compensation.Z. Huang, Q. Luo, and Y. Inoue. ISCAS, page 4069-4072. IEEE, (2010)

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Disambiguation of "Inoue, Yasuaki"

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Capacitance and Yield Evaluations Using a 90-nm Process Technology Based on the Dense Power-Ground Interconnect Architecture.

Please choose a person to relate this publication to

Yasuaki Saigusa

Heide Inoue

Tomoyuki Inoue

Hiroko Inoue

Norman Inoue

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Inoue, Yasuaki"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Capacitance and Yield Evaluations Using a 90-nm Process Technology Based on the Dense Power-Ground Interconnect Architecture.

Please choose a person to relate this publication to

Yasuaki Saigusa

Heide Inoue

Tomoyuki Inoue

Hiroko Inoue

Norman Inoue

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Capacitance and Yield Evaluations Using a 90-nm Process Technology Based on the Dense Power-Ground Interconnect Architecture.