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Disambiguation of "Masuda, Hiroo"

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Formula-Based Method for Capacitance Extraction of Interconnects with Dummy Fills.

, , , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 89-A (4): 847-855 (2006)

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Hiroo Furuuchi

Hiroo Furuuchi

Hiroo Furuuchi

Hiroo Furuuchi

 

Other publications of authors with the same name

Fast On-Chip Inductance Extraction of VLSI Including Angled Interconnects., , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 86-A (4): 841-845 (2003)A New Design-Centering Methodology for VLSI Device Development., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 6 (3): 452-461 (1987)Crosstalk delay analysis of a 0.13-μm node test chip and precise gate-level simulation technology., , , , , , and . IEEE J. Solid State Circuits, 38 (5): 702-708 (2003)Comprehensive Matching Characterization of Analog CMOS Circuits., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 92-A (4): 966-975 (2009)Impact of Self-Heating in Wire Interconnection on Timing., , , , , , , , , and 2 other author(s). IEICE Trans. Electron., 93-C (3): 388-392 (2010)Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations., , , , , , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 92-A (4): 990-997 (2009)Challenge: variability characterization and modeling for 65- to 90-nm processes., , , and . CICC, page 593-599. IEEE, (2005)Determination of Interconnect Structural Parameters for Best- and Worst-Case Delays., , , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 89-A (4): 856-864 (2006)Concise Modeling of Transistor Variations in an LSI Chip and Its Application to SRAM Cell Sensitivity Analysis., , and . IEICE Trans. Electron., 91-C (4): 647-654 (2008)Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance., , , , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 88-A (12): 3453-3462 (2005)