( en | de | ru )

 

Disambiguation of "Shieh, Ming-Der"

Author of the publication

copydeleteadd this publication to your clipboard
Efficient path metric access for reducing interconnect overhead in Viterbi decoders.

, , , and . ISCAS, IEEE, (2006)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Ming-Yan Shieh

Shu-Mei Shieh

Woei-Chyang Shieh

Jin-Wien Shieh

Pi-Er Shieh

 

Other publications of authors with the same name

Design of a High-Speed Square Generator., and . IEEE Trans. Computers, 47 (9): 1021-1026 (1998)A low-latency turbo decoding scheme for diversities-based communication systems., , , and . ICSPCS, page 1-6. IEEE, (2012)A VLSI architecture of fast high-radix modular multiplication for RSA cryptosystem., , , , and . ISCAS (1), page 500-503. IEEE, (1999)A novel adaptive algorithm and VLSI design for frequency detection in noisy environment based on adaptive IIR filter., , , and . ISCAS (4), page 446-449. IEEE, (2001)An efficient countermeasure against power attacks for ECC over GF(p)., , and . ISCAS, page 814-817. IEEE, (2014)VLSI architecture of extended in-place path metric update for Viterbi decoders., , , and . ISCAS (4), page 206-209. IEEE, (2001)Efficient path metric access for reducing interconnect overhead in Viterbi decoders., , , and . ISCAS, IEEE, (2006)Low-complexity Reed-Solomon decoder for optical communications., , and . ISCAS, page 4173-4176. IEEE, (2010)A New Modular Exponentiation Architecture for Efficient Design of RSA Cryptosystem., , , and . IEEE Trans. Very Large Scale Integr. Syst., 16 (9): 1151-1161 (2008)Efficient Memory-Addressing Algorithms for FFT Processor Design., , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (10): 2162-2172 (2015)