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Disambiguation of "Hidaka, Yasuo"

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Design and Analysis of Energy-Efficient Reconfigurable Pre-Emphasis Voltage-Mode Transmitters.

, , , and . IEEE J. Solid State Circuits, 48 (8): 1898-1909 (2013)

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Yasuo Kamata

Yasuo Tokunaga

Yasuo Nakayama

 

Other publications of authors with the same name

Architecture of parallel management kernel for PIE64., , and . Future Gener. Comput. Syst., 10 (1): 29-43 (1994)A 4-channel 10.3Gb/s transceiver with adaptive phase equalizer for 4-to-41dB loss PCB channel., , , , , , , , , and . ISSCC, page 346-348. IEEE, (2011)A 4-Channel 1.25-10.3 Gb/s Backplane Transceiver Macro With 35 dB Equalizer and Sign-Based Zero-Forcing Adaptive Control., , , , , and . IEEE J. Solid State Circuits, 44 (12): 3547-3559 (2009)Architecture of Parallel Management Kernel for PIE64., , and . PARLE, volume 605 of Lecture Notes in Computer Science, page 685-700. Springer, (1992)A 4-channel 10.3Gb/s backplane transceiver macro with 35dB equalizer and sign-based zero-forcing adaptive control., , , , , and . ISSCC, page 188-189. IEEE, (2009)Design Consideration of 6.25 Gbps Signaling for High-Performance Server., , , , , , and . ASP-DAC, page 854-857. IEEE Computer Society, (2007)32Gb/s 28nm CMOS time-interleaved transmitter compatible with NRZ receiver with DFE., , , , , , , , and . ISSCC, page 40-41. IEEE, (2013)A Static Load Partitioning Method based on Execution Profile for Committed Choice Languages., , , and . ISLP, page 470-484. MIT Press, (1991)Design and Analysis of Energy-Efficient Reconfigurable Pre-Emphasis Voltage-Mode Transmitters., , , and . IEEE J. Solid State Circuits, 48 (8): 1898-1909 (2013)Multiple Threads in Cyclic Register Windows., , and . ISCA, page 131-142. ACM, (1993)