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Errata Erratum to Ä 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS"., , , , , , and . IEEE J. Solid State Circuits, 55 (4): 1124 (2020)40-Gb/s circuits built from a 120-GHz fT SiGe technology., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 37 (9): 1106-1114 (2002)A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links., , , , , , , , , and 14 other author(s). IEEE J. Solid State Circuits, 58 (4): 1074-1086 (2023)Low-power multi-GHz and multi-Gb/s SiGe BiCMOS circuits., , , and . Proc. IEEE, 88 (10): 1572-1582 (2000)29.1 A 64Gb/s 1.4pJ/b NRZ optical-receiver data-path in 14nm CMOS FinFET., , , , , , , , , and 6 other author(s). ISSCC, page 482-483. IEEE, (2017)132-Gb/s 4: 1 multiplexer in 0.13-μm SiGe-bipolar technology.. IEEE J. Solid State Circuits, 39 (12): 2403-2407 (2004)A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver With Low-Latency Digital CDR in 14-nm CMOS FinFET., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 53 (4): 1227-1237 (2018)A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 52 (12): 3458-3473 (2017)A 10-Gb/s two-dimensional eye-opening monitor in 0.13-μm standard CMOS., , , , and . IEEE J. Solid State Circuits, 40 (12): 2689-2699 (2005)Introduction to the Special Issue on the 2017 IEEE International Solid-State Circuits Conference., , , , and . IEEE J. Solid State Circuits, 52 (12): 3115-3118 (2017)