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Disambiguation of "Devanathan, V. R."

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ProWATCh: A Proactive Cross-Layer Workload-Aware Temperature Management Framework for Low-Power Chip Multi-Processors.

, , , , , , and . ACM J. Emerg. Technol. Comput. Syst., 12 (3): 22:1-22:25 (2015)

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Vasudharani Devanathan

Devanathan Raghunathan

V Saile

V Geoffroy

V Wittwer

 

Other publications of authors with the same name

Best is the Enemy of Good: Design Techniques for Low Power Tunable Approximate Application Specific Integrated Chips Targeting Media-Based Applications., , , and . J. Low Power Electron., 11 (2): 133-148 (2015)Variation-Tolerant, Power-Safe Pattern Generation., , and . IEEE Des. Test Comput., 24 (4): 374-384 (2007)Towards adaptive test of multi-core RF SoCs., , , , , and . DATE, page 743-748. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Towards effective and compression-friendly test of memory interface logic., , , and . ITC, page 124-133. IEEE Computer Society, (2010)A Framework for Concurrency Control in Real-Time Distributed Collaboration for Mobile Systems., , and . ICDCS Workshops, page 488-492. IEEE Computer Society, (2003)ProCA: Progressive Configuration Aware Design Methodology for Low Power Stochastic ASICs., , , , and . VLSID, page 342-347. IEEE Computer Society, (2014)Novel Bi-partitioned Scan Architecture to Improve Transition Fault Coverage.. Asian Test Symposium, page 300-305. IEEE Computer Society, (2005)Interactive presentation: On power-profiling and pattern generation for power-safe scan tests., , and . DATE, page 534-539. EDA Consortium, San Jose, CA, USA, (2007)Methodology for low power test pattern generation using activity threshold control logic., , and . ICCAD, page 526-529. IEEE Computer Society, (2007)Thermal-Safe Dynamic Test Scheduling Method Using On-Chip Temperature Sensors for 3D MPSoCs., , , , and . J. Low Power Electron., 8 (5): 684-695 (2012)