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On efficient generation of instruction sequences to test for delay defects in a processor.

, , , and . ACM Great Lakes Symposium on VLSI, page 279-284. ACM, (2008)

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ACCE: Automatic correction of control-flow errors., , and . ITC, page 1-10. IEEE Computer Society, (2007)Cache-resident self-testing for I/O circuitry., , , and . ITC, page 1-8. IEEE Computer Society, (2009)Comparing the effectiveness of cache-resident tests against cycleaccurate deterministic functional patterns., , , and . ITC, page 1-8. IEEE Computer Society, (2014)Automatic generation of instruction sequences targeting hard-to-detect structural faults in a processor., , and . ITC, page 1-9. IEEE Computer Society, (2006)Automatic Generation of Instructions to Robustly Test Delay Defects in Processors., , , and . ETS, page 173-178. IEEE Computer Society, (2007)On efficient generation of instruction sequences to test for delay defects in a processor., , , and . ACM Great Lakes Symposium on VLSI, page 279-284. ACM, (2008)On Complementing Nondeterministic Büchi Automata., , , and . CHARME, volume 2860 of Lecture Notes in Computer Science, page 96-110. Springer, (2003)Fair Simulation Minimization., , and . CAV, volume 2404 of Lecture Notes in Computer Science, page 610-624. Springer, (2002)Functionally valid gate-level peak power estimation for processors., , , and . ISQED, page 753-758. IEEE Computer Society, (2009)