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On efficient generation of instruction sequences to test for delay defects in a processor.

, , , and . ACM Great Lakes Symposium on VLSI, page 279-284. ACM, (2008)

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Research in Reliable VLSI Architectures at the University of Illinois.. FJCC, page 890-893. IEEE Computer Society, (1986)Design of Test Pattern Generators for Built-In Test., , and . ITC, page 315-319. IEEE Computer Society, (1984)An oscillation-based test structure for timing information extraction., , , and . VTS, page 74-79. IEEE Computer Society, (2012)Comparison and Diagnosis of Large Replicated Files., , and . IEEE Trans. Software Eng., 13 (1): 15-22 (1987)Design and evaluation of fault tolerance techniques for highly parallel architectures.. Great Lakes Symposium on VLSI, IEEE, (1991)Abstraction of data path registers for multilevel verification of large circuits., , , and . Great Lakes Symposium on VLSI, page 11-14. IEEE, (1994)Forward Recovery Using Checkpointing in Parallel Systems., , and . ICPP (1), page 272-275. Pennsylvania State University Press, (1990)Average Interconnection Length and Interconnection Distribution Based on Rent's Rule., and . DAC, page 574-577. ACM Press, (1989)A Novel Approach to Accurate Timing Verification Using RTL Descriptions., and . DAC, page 638-641. ACM Press, (1989)A low latency and low power dynamic Carry Save Adder., , , , , , , and . ISCAS (2), page 477-480. IEEE, (2004)