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Implementation of the 65nm Cell Broadband Engine., , , , , , , , , and 4 other author(s). CICC, page 717-720. IEEE, (2007)Debug of the CELL Processor: Moving the Lab into Silicon., , , and . ITC, page 1-9. IEEE Computer Society, (2006)Testability features of the first-generation CELL processor., , , , and . ITC, page 9. IEEE Computer Society, (2005)Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor., , , , , , , , , and 14 other author(s). IEEE J. Solid State Circuits, 41 (1): 179-196 (2006)Cell Broadband Engine Debugging for Unknown Events., and . IEEE Des. Test Comput., 24 (5): 486-493 (2007)Cell Broadband Engine processor: Design and implementation., , and . IBM J. Res. Dev., 51 (5): 545-558 (2007)A Circuit for Reducing Large Transient Current Effects on Processor Power Grids., , , , , and . ISSCC, page 2238-2245. IEEE, (2006)Migration of Cell Broadband Engine from 65nm SOI to 45nm SOI., , , , , , , , , and 15 other author(s). ISSCC, page 86-87. IEEE, (2008)Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor., , , , , , , , , and 13 other author(s). ASP-DAC, page 871-878. IEEE, (2006)The design methodology and implementation of a first-generation CELL processor: a multi-core SoC., , , , , , , , , and 8 other author(s). CICC, page 45-49. IEEE, (2005)