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True hardware random number generation implemented in the 32-nm SOI POWER7+ processor., , , , , , , and . IBM J. Res. Dev., (2013)Implementation of the Cell Broadband Engine™ in 65 nm SOI Technology Featuring Dual Power Supply SRAM Arrays Supporting 6 GHz at 1.3 V., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 43 (1): 163-171 (2008)Implementation of the CELL Broadband Engine in a 65nm SOI Technology Featuring Dual-Supply SRAM Arrays Supporting 6GHz at 1.3V., , , , , , , , , and 2 other author(s). ISSCC, page 322-606. IEEE, (2007)Migration of Cell Broadband Engine from 65nm SOI to 45nm SOI., , , , , , , , , and 15 other author(s). ISSCC, page 86-87. IEEE, (2008)The circuit design of the synergistic processor element of a CELL processor., , , , , , , , , and 3 other author(s). ICCAD, page 111-117. IEEE Computer Society, (2005)Power-Conscious Design of the Cell Processor's Synergistic Processor Element., , , , and . IEEE Micro, 25 (5): 10-18 (2005)Low-Power Design Approach of 11FO4 256-Kbyte Embedded SRAM for the Synergistic Processor Element of a Cell Processor., , , , , , , , and . IEEE Micro, 25 (5): 30-38 (2005)A fully pipelined single-precision floating-point unit in the synergistic processor element of a CELL processor., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 41 (4): 759-771 (2006)Cell Broadband Engine Processor Design Methodology., , , , , , , , and . CICC, page 711-716. IEEE, (2007)