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A Dual-Core Multi-Threaded Xeon Processor with 16MB L3 Cache.

, , , , и . ISSCC, стр. 315-324. IEEE, (2006)

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Simon M M Laimer

Simon M Seuren

Simon M Schädler

Simon M Ametamey

Simon M Lenz

 

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A 65-nm Dual-Core Multithreaded Xeon® Processor With 16-MB L3 Cache., , , , , , , , , и 2 other автор(ы). IEEE J. Solid State Circuits, 42 (1): 17-25 (2007)A 45nm 8-core enterprise Xeon® processor., , , , , , , , и . ISSCC, стр. 56-57. IEEE, (2009)Itanium processor clock design., , , , и . ISPD, стр. 94-98. ACM, (2000)A 22 nm 15-Core Enterprise Xeon® Processor Family., , , , , , , , , и . IEEE J. Solid State Circuits, 50 (1): 35-48 (2015)A Dual-Core Multi-Threaded Xeon Processor with 16MB L3 Cache., , , , и . ISSCC, стр. 315-324. IEEE, (2006)5.4 Ivytown: A 22nm 15-core enterprise Xeon® processor family., , , , , , , , , и . ISSCC, стр. 102-103. IEEE, (2014)Analog VLSI neural networks for impact signal processing., , , и . IEEE Micro, 12 (6): 34-45 (1992)SkyLake-SP: A 14nm 28-Core xeon® processor., , , , , , , , , и 2 other автор(ы). ISSCC, стр. 34-36. IEEE, (2018)A 45 nm 8-Core Enterprise Xeon¯ Processor., , , , , , , , , и . IEEE J. Solid State Circuits, 45 (1): 7-14 (2010)Power reduction techniques for an 8-core xeon® processor., , , , , , , , , и . ESSCIRC, стр. 340-343. IEEE, (2009)