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Switching Event Detection and Self-Termination Programming Circuit for Energy Efficient ReRAM Memory Arrays., , , , , , , , и . IEEE Trans. Circuits Syst. II Express Briefs, 66-II (5): 748-752 (2019)Sub-pJ consumption and short latency time in RRAM arrays for high endurance applications., , , , , , , , , и 2 other автор(ы). IRPS, стр. 2-1. IEEE, (2018)High speed and high-area efficiency non-volatile look-up table design based on magnetic tunnel junction., , , и . NVMTS, стр. 1-4. IEEE, (2017)OTS selector devices: Material engineering for switching performance., , , , , , , , и . ICICDT, стр. 113-116. IEEE, (2018)Low Power In-Memory Implementation of Ternary Neural Networks with Resistive RAM-Based Synapse., , , , , , , , и . AICAS, стр. 136-140. IEEE, (2020)Digital Biologically Plausible Implementation of Binarized Neural Networks with Differential Hafnium Oxide Resistive Memory Arrays., , , , , , , и . CoRR, (2019)Write Termination Circuits for RRAM: A Holistic Approach From Technology to Application Considerations., , , , , , , , , и . IEEE Access, (2020)In-Memory Resistive RAM Implementation of Binarized Neural Networks for Medical Applications., , , , , , , и . DATE, стр. 690-695. IEEE, (2020)Elucidating 1S1R operation to reduce the read voltage margin variability by stack and programming conditions optimization., , , , , , , , , и 4 other автор(ы). IRPS, стр. 1-6. IEEE, (2021)High density SOT-MRAM memory array based on a single transistor., , , и . NVMTS, стр. 1-3. IEEE, (2018)