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3D resistive RAM cell design for high-density storage class memory - a review.

B. Hudec, C. Hsu, I. Wang, W. Lai, C. Chang, T. Wang, K. Fröhlich, C. Ho, C. Lin, and T. Hou. Sci. China Inf. Sci., 59 (6): 061403:1-061403:21 (2016)

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Tuo Li

Biguang Tuo

Rudolf Tuor

Xihe Tuo

Tuo Liu

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SLIM: Simultaneous Logic-in-Memory Computing Exploiting Bilayer Analog OxRAM Devices.S. Kingra, V. Parmar, C. Chang, B. Hudec, T. Hou, and M. Suri. CoRR, (2018)Methodology for Realizing VMM with Binary RRAM Arrays: Experimental Demonstration of Binarized-ADALINE using OxRAM Crossbar.S. Kingra, V. Parmar, S. Negi, S. Khan, B. Hudec, T. Hou, and M. Suri. ISCAS, page 1-5. IEEE, (2020)Roadmap to Neuromorphic Computing with Emerging Technologies.A. Mehonic, D. Ielmini, K. Roy, O. Mutlu, S. Kvatinsky, T. Serrano-Gotarredona, B. Linares-Barranco, S. Spiga, S. Savelev, A. Balanov and 42 other author(s). CoRR, (2024)Phase and Carrier Polarity Control of Sputtered MoTe2 by Plasma-induced Defect Engineering.C. Lin, H. Hsu, and T. Hou. DRC, page 1-2. IEEE, (2020)A Multi-Bit Near-RRAM based Computing Macro with Highly Computing Parallelism for CNN Application.K. Lin, H. Zuo, H. Wang, Y. Huang, C. Wu, Y. Guo, S. Jou, T. Hou, and T. Chang. DATE, page 1-6. IEEE, (2024)Optimizing Incremental Step Pulse Programming for RRAM Through Device-Circuit Co-Design.J. Liu, T. Wu, and T. Hou. IEEE Trans. Circuits Syst. II Express Briefs, 65-II (5): 617-621 (2018)FPCIM: A Fully-Parallel Robust ReRAM CIM Processor for Edge AI Devices.Y. Guo, W. Lin, T. Hou, and T. Chang. ISCAS, page 1-5. IEEE, (2023)A 48 TOPS and 20943 TOPS/W 512kb Computation-in-SRAM Macro for Highly Reconfigurable Ternary CNN Acceleration.C. Lin, F. Tsai, J. Su, S. Li, T. Chang, S. Sheu, W. Lo, S. Chang, C. Wu, and T. Hou. A-SSCC, page 1-3. IEEE, (2021)Low power nonvolatile SRAM circuit with integrated low voltage nanocrystal PMOS Flash.S. Rajwade, W. Yu, S. Xu, T. Hou, G. Suh, and E. Kan. SoCC, page 461-466. IEEE, (2010)Mitigating Effects of Non-ideal Synaptic Device Characteristics for On-chip Learning.P. Chen, B. Lin, I. Wang, T. Hou, J. Ye, S. Vrudhula, J. sun Seo, Y. Cao, and S. Yu. ICCAD, page 194-199. IEEE, (2015)

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Disambiguation of "Hou, Tuo-Hung"

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3D resistive RAM cell design for high-density storage class memory - a review.

Please choose a person to relate this publication to

Tuo Li

Biguang Tuo

Rudolf Tuor

Xihe Tuo

Tuo Liu

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Hou, Tuo-Hung"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 3D resistive RAM cell design for high-density storage class memory - a review.

Please choose a person to relate this publication to

Tuo Li

Biguang Tuo

Rudolf Tuor

Xihe Tuo

Tuo Liu

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
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Chicago
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3D resistive RAM cell design for high-density storage class memory - a review.