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Cross-matching caches: Dynamic timing calibration and bit-level timing-failure mask caches to reduce timing discrepancies with low voltage processors.

, , , , , and . Integr., (2016)

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Cross-matching caches: Dynamic timing calibration and bit-level timing-failure mask caches to reduce timing discrepancies with low voltage processors., , , , , and . Integr., (2016)ULV-Turbo Cache for an Instantaneous Performance Boost on Asymmetric Architectures., , , , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (12): 3341-3354 (2017)Variation-aware and adaptive-latency accesses for reliable low voltage caches., , , , , , , , and . VLSI-SoC, page 358-363. IEEE, (2013)Zero-Counting and Adaptive-Latency Cache Using a Voltage-Guardband Breakthrough for Energy-Efficient Operations., , , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 63-II (10): 969-973 (2016)The reflexive printer: toward making sense of perceived drawbacks in technology-mediated reminiscence., , , , and . Conference on Designing Interactive Systems, page 995-1004. ACM, (2014)The reflexive printer: embodying personal memory for social provocation., , , , and . Conference on Designing Interactive Systems (Companion Volume), page 97-100. ACM, (2014)A latency-elastic and fault-tolerant cache for improving performance and reliability on low voltage operation., , , and . VLSI-DAT, page 1-4. IEEE, (2015)A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS., , , , , , , , , and 8 other author(s). ISSCC, page 158-159. IEEE, (2013)