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Disambiguation of "Joshi, Rajiv V."

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Analysis of the effect of the gate oxide breakdown on SRAM stability.

, , , , , , , , , and . Microelectron. Reliab., 42 (9-11): 1445-1448 (2002)

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Rajiv Trehan

Rajiv Kumar

Paneerselvam Rajiv

Jidnyasa Joshi

Rajiv Grover

 

Other publications of authors with the same name

The resilience wall: Cross-layer solution strategies., , , , , , , , , and 3 other author(s). VLSI-DAT, page 1-11. IEEE, (2014)Guest Editorial Emerging Memories - Technology, Architecture and Applications (Second Issue)., , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 6 (3): 261-264 (2016)Overview of Circuits, Systems, and Applications of Spintronics., , , , , , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 6 (3): 265-278 (2016)3-D-TCAD-Based Parasitic Capacitance Extraction for Emerging Multigate Devices and Circuits., , and . IEEE Trans. Very Large Scale Integr. Syst., 21 (11): 2094-2105 (2013)A scannable pulse-to-static conversion register array for self-timed circuits., , and . IEEE J. Solid State Circuits, 35 (1): 125-128 (2000)A 500-MHz, 32-word×64-bit, eight-port self-resetting CMOS register file., , and . IEEE J. Solid State Circuits, 34 (1): 56-67 (1999)Phase Noise Analysis of Separately Driven Ring Oscillators., , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 69 (11): 4415-4428 (2022)Group LARS-Based Iterative Reweighted Least Squares Methodology for Efficient Statistical Modeling of Memory Designs., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (12): 5722-5726 (2022)New optimal design strategies and analysis of ultra-low leakage circuits for nano-scale SOI technology., , , , and . ISLPED, page 168-171. ACM, (2003)Hierarchical Memory System With STT-MRAM and SRAM to Support Transfer and Real-Time Reinforcement Learning in Autonomous Drones., , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 9 (3): 485-497 (2019)