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Disambiguation of "Chang, Kuo-Chiang"

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Separate Clock Network Voltage for Correcting Random Errors in ULV Clocked Storage Cells.

, , , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 61-II (12): 947-951 (2014)

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Chao-Kuo Chiang

Yi-Chang Chiang

Kuo-Wen Chang

Ting-Kuo Chang

Johannes Kuo-huie Chiang

 

Other publications of authors with the same name

MORAS: An energy-scalable system using adaptive voltage scaling., , , , and . VLSI-DAT, page 1-4. IEEE, (2018)An ultra-low voltage hearing aid chip using variable-latency design technique., , , , , and . ISCAS, page 2543-2546. IEEE, (2014)Complexity-effective auditory compensation with a controllable filter for digital hearing aids., , , and . ASP-DAC, page 557-558. IEEE, (2012)Design and implementation of 18-band Quasi-ANSI S1.11 1/3-octave filter bank for digital hearing aids., , , and . VLSI-DAT, page 1-4. IEEE, (2012)A low power hearing aid computing platform using lightweight processing elements., , , and . ISCAS, page 2785-2788. IEEE, (2012)Complexity-effective dynamic range compression for digital hearing aids., , , and . ISCAS, page 2378-2381. IEEE, (2010)A Low-Error, Cost-Efficient Design Procedure for Evaluating Logarithms to Be Used in a Logarithmic Arithmetic Processor., , , , and . IEEE Trans. Computers, 65 (4): 1158-1164 (2016)An object tracking scheme for wireless sensor networks using data mining mechanism., , and . NOMS, page 526-529. IEEE, (2012)10-ms 18-Band Quasi-ANSI S1.11 1/3-Octave Filter Bank for Digital Hearing Aids., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 60-I (3): 638-649 (2013)Configurable Deep Learning Accelerator with Bitwise-accurate Training and Verification., , , and . VLSI-DAT, page 1-4. IEEE, (2022)