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MORAS: An energy-scalable system using adaptive voltage scaling.

K. Chang, S. Luo, C. Huang, J. Peng, и Y. Chu. VLSI-DAT, стр. 1-4. IEEE, (2018)

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Hua Yuan

Chi-Hua Chu

Chia-hua Chu

Xiugan Yuan

Jing Yuan

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Collaborative voltage scaling with online STA and variable-latency datapath.T. Lin, P. Hsiao, C. Lin, S. Kuo, C. Lin, Y. Kuo, C. Liu, и Y. Chu. ACM Great Lakes Symposium on VLSI, стр. 347-352. ACM, (2010)Separate Clock Network Voltage for Correcting Random Errors in ULV Clocked Storage Cells.S. Luo, K. Chang, M. Chen, C. Huang, Y. Chiu, P. Chen, L. Cheng, C. Liu, и Y. Chu. IEEE Trans. Circuits Syst. II Express Briefs, 61-II (12): 947-951 (2014)PVT-aware digital controlled voltage regulator design for ultra-low-power (ULP) DVFS systems.P. Wu, Y. Kuo, C. Wu, C. Chuang, Y. Chu, и W. Hwang. SoCC, стр. 136-139. IEEE, (2014)Low-Voltage Low-Power CMOS True-Single-Phase Clocking Scheme with Locally Asynchronous Logic Circuits.H. Huang, J. Wang, Y. Chu, T. Wu, K. Cheng, и C. Wu. ISCAS, стр. 1572-1575. IEEE, (1995)A Sub-0.3 V Area-Efficient L-Shaped 7T SRAM With Read Bitline Swing Expansion Schemes Based on Boosted Read-Bitline, Asymmetric-VTH Read-Port, and Offset Cell VDD Biasing Techniques.M. Chang, M. Chen, L. Chen, S. Yang, Y. Kuo, J. Wu, H. Su, Y. Chu, W. Wu, T. Yang и 1 other автор(ы). IEEE J. Solid State Circuits, 48 (10): 2558-2569 (2013)A dual-edged triggered explicit-pulsed level converting flip-flop with a wide operation range.M. Chen, M. Chang, P. Wu, Y. Kuo, C. Yang, Y. Chu, и W. Hwang. SoCC, стр. 92-97. IEEE, (2013)A Large Sigma V TH /VDD Tolerant Zigzag 8T SRAM With Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme.J. Wu, Y. Chen, M. Chang, P. Chou, C. Chen, H. Liao, M. Chen, Y. Chu, W. Wu, и H. Yamauchi. IEEE J. Solid State Circuits, 46 (4): 815-827 (2011)A 260mV L-shaped 7T SRAM with bit-line (BL) Swing expansion schemes based on boosted BL, asymmetric-VTH read-port, and offset cell VDD biasing techniques.M. Chen, L. Chen, M. Chang, S. Yang, Y. Kuo, J. Wu, M. Ho, H. Su, Y. Chu, W. Wu и 2 other автор(ы). VLSIC, стр. 112-113. IEEE, (2012)Energy-efficient RISC design with on-demand circuit-level timing speculation.T. Lin, Y. Kuo, Y. Tsai, T. Shyu, и Y. Chu. ASP-DAC, стр. 477-478. IEEE, (2012)A 3 MHz-to-1.8 GHz 94 μW-to-9.5 mW 0.0153-mm2 all-digital delay-locked loop in 65-nm CMOS.C. Cheng, J. Wang, P. Chou, S. Chen, C. Sun, Y. Chu, и T. Yang. A-SSCC, стр. 361-364. IEEE, (2014)

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