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Disambiguation of "Chang, Soon-Jyh"

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An Unbounded Frequency Detection Mechanism for Continuous-Rate CDR Circuits.

, , , and . IEEE Trans. Circuits Syst. II Express Briefs, 64-II (5): 500-504 (2017)

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Soon-Nan Chang

Il-Soon Chang

Chang-Soon Park

Nithya Soonthornpanich

Sukanya Soonagahalli Lava

 

Other publications of authors with the same name

A Low Energy Consumption 10-Bit 100kS/s SAR ADC with Timing Control Adaptive Window., , , and . ISCAS, page 1-4. IEEE, (2018)An 8-bit 400-MS/s calibration-free SAR ADC with a pre-amplifier-only comparator., , , , and . VLSI-DAT, page 1-4. IEEE, (2017)A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling., , , , , , , , , and 3 other author(s). ASP-DAC, page 17-18. IEEE, (2016)An area- and power-efficient half-rate clock and data recovery circuit., , , , , and . ISCAS, page 2129-2132. IEEE, (2014)Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 21 (4): 624-635 (2013)A 9-Bit 150-MS/s Subrange ADC Based on SAR Architecture in 90-nm CMOS., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 60-I (3): 570-581 (2013)A Low-Power Mixed-Architecture ADC with Time-Interleaved Correlated Double Sampling Technique and Power-Efficient Back-End Stages., and . IEICE Trans. Electron., 94-C (1): 89-101 (2011)Histogram Based Testing Strategy for ADC., , and . ATS, page 51-54. IEEE, (2006)A 1.6-GS/s 8b Flash-SAR Time-Interleaved ADC with Top-Plate Residue Based Gain Calibration., and . ISCAS, page 1-5. IEEE, (2021)A Physically Unclonable Function Embedded in a SAR ADC., and . ITC-Asia, page 85-89. IEEE, (2022)