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Disambiguation of "Hariyama, Masanori"

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Switch Block Architecture for Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals.

, , and . ISMVL, page 17. IEEE Computer Society, (2006)

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Benchmarks for FPGA-Targeted High-Level-Synthesis., , and . CANDAR, page 232-238. IEEE, (2019)Implementation of an FPGA-Oriented Complex Number Computation Library Using Intel OneAPI DPC++., , and . MWSCAS, page 1-4. IEEE, (2022)Hardware-oriented succinct-data-structure based on block-size-constrained compression., , and . SoCPaR, page 136-140. IEEE, (2015)Non-Volatile Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals., , , and . ERSA, page 309-310. CSREA Press, (2008)Switch Block Architecture for Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals., , and . ISMVL, page 17. IEEE Computer Society, (2006)Low-Power Field-Programmable VLSI Processor Using Dynamic Circuits., , and . ISVLSI, page 243-248. IEEE Computer Society, (2004)Efficient data transfer scheme using word-pair-encoding-based compression for large-scale text-data processing., , , and . APCCAS, page 639-642. IEEE, (2014)Memory Allocation Exploiting Temporal Locality for Reducing Data-Transfer Bottlenecks in Heterogeneous Multicore Processors., , , and . IEEE Trans. Circuits Syst. Video Techn., 21 (10): 1453-1466 (2011)Genetic Approach to Minimizing Energy Consumption of VLSI Processors Using Multiple Supply Voltages., , and . IEEE Trans. Computers, 54 (6): 642-650 (2005)Advanced Devices and Architectures., , and . Principles and Structures of FPGAs, Springer, (2018)