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Identification and Frequency Estimation of Feedback Bridging Faults Generating Logical Oscillation in CMOS Circuits., , и . IEICE Trans. Inf. Syst., 87-D (3): 571-579 (2004)On Detecting Delay Faults Using Time-to-Digital Converter Embedded in Boundary Scan., , , и . IEICE Trans. Inf. Syst., 96-D (9): 1986-1993 (2013)Fault Detection of Combinational Circuits Based on Supply Current., , , и . ITC, стр. 374-380. IEEE Computer Society, (1988)Efficient test length reduction techniques for interposer-based 2.5D ICs., , , , и . VLSI-DAT, стр. 1-4. IEEE, (2014)Address Scrambling and Data Inversion Techniques for Yield Enhancement of NROM-Based ROMs., , , и . IEEE Trans. Computers, 64 (5): 1230-1240 (2015)A built-in test circuit for open defects at interconnects between dies in 3D ICs., , , , и . 3DIC, стр. 1-5. IEEE, (2011)Current Testable Design of Resistor String DACs., , , , и . ATS, стр. 399-403. IEEE, (2007)New Class of Tests for Open Faults with Considering Adjacent Lines., , , , , , и . Asian Test Symposium, стр. 301-306. IEEE Computer Society, (2009)Test Data Reduction for BIST-Aided Scan Test Using Compatible Flip-Flops and Shifting Inverter Code., , и . Asian Test Symposium, стр. 163-166. IEEE Computer Society, (2010)Test Time Reduction for I DDQ Testing by Arranging Test Vectors., , и . Asian Test Symposium, стр. 423-428. IEEE Computer Society, (2002)