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Disambiguation of "Noda, Kenji"

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A Study of Capture-Safe Test Generation Flow for At-Speed Testing.

, , , , , , , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 93-A (7): 1309-1318 (2010)

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Teruhisa Noda

Tatsuhiko Noda

Shigeru Noda

Norihiro Noda

Norihiro Noda

 

Other publications of authors with the same name

A 500-MHz 4-Mb CMOS pipeline-burst cache SRAM with point-to-point noise reduction coding I/O., , , , , , , , , and . IEEE J. Solid State Circuits, 32 (11): 1758-1765 (1997)Effective IR-drop reduction in at-speed scan testing using Distribution-Controlling X-Identification., , , , , , , , and . ICCAD, page 52-58. IEEE Computer Society, (2008)Session 16 - Embedded memory., and . CICC, IEEE, (2008)A novel post-ATPG IR-drop reduction scheme for at-speed scan testing in broadcast-scan-based test compression environment., , , , , , , and . ICCAD, page 97-104. ACM, (2009)A 16-Mb 400-MHz loadless CMOS four-transistor SRAM macro., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 35 (11): 1631-1640 (2000)An ultra-high-density high-speed loadless four-transistor SRAM macro with a dual-layered twisted bit-line and a triple-well shield., , , , , , , , , and 2 other author(s). CICC, page 283-286. IEEE, (2000)A High-Level Synthesis Method for Weakly Testable Data Paths., , , , and . Asian Test Symposium, page 40-45. IEEE Computer Society, (1998)A Capture-Safe Test Generation Scheme for At-Speed Scan Testing., , , , , , , , , and 1 other author(s). ETS, page 55-60. IEEE Computer Society, (2008)A Study of Capture-Safe Test Generation Flow for At-Speed Testing., , , , , , , , , and 1 other author(s). IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 93-A (7): 1309-1318 (2010)Distribution-Controlled X-Identification for Effective Reduction of Launch-Induced IR-Drop in At-Speed Scan Testing., , , , , , , , and . IEICE Trans. Inf. Syst., 94-D (6): 1216-1226 (2011)