( en | de | ru )

 

Disambiguation of "Urard, Pascal"

Author of the publication

copydeleteadd this publication to your clipboard
Silicon 3D-integration technology and systems.

, , , , , , , , , and . ISSCC, page 510-511. IEEE, (2010)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Pascal Häller

Pascal Bastian

Pascal Bihler

Pascal Siegers

Pascal Vogel

 

Other publications of authors with the same name

Low-Complexity, Low-Memory EMS Algorithm for Non-Binary LDPC Codes., , , , and . ICC, page 671-676. IEEE, (2007)A 135Mbps DVB-S2 compliant codec based on 64800-bit LDPC and BCH codes (ISSCC paper 24.3)., , , , , , and . DAC, page 547-548. ACM, (2005)Functional Equivalence Verification Tools in High-Level Synthesis Flows., , , and . IEEE Des. Test Comput., 26 (4): 88-95 (2009)Macrocell Builder: IP-Block-Based Design Environment for High-Throughput VLSI Dedicated Digital Signal Processing Systems., , , and . EURASIP J. Adv. Signal Process., (2006)Quantization Modes for Neural Network Inference: ASIC Implementation Trade-offs., , , , , , and . IJCNN, page 1-8. IEEE, (2023)22.5 A 1.62GS/s time-interleaved SAR ADC with digital background mismatch calibration achieving interleaving spurs below 70dBFS., , , , , , , , , and . ISSCC, page 386-388. IEEE, (2014)A 17.5-to-20.94GHz and 35-to-41.88GHz PLL in 65nm CMOS for wireless HD applications., , , , , , , , and . ISSCC, page 252-253. IEEE, (2010)An Efficient Methodology and Semi-Automated Flow for Design and Validation of Complex Digital Signal Processing ASICS Macro-Cells., , , , and . IEEE International Workshop on Rapid System Prototyping, page 56-63. IEEE Computer Society, (2003)A Nano quiescent Current Power Management for Autonomous Wireless Sensor Network., , , , , and . ICECS, page 815-818. IEEE, (2013)Ultra-wide body-bias range LDPC decoder in 28nm UTBB FDSOI technology., , , , , , , , , and 4 other author(s). ISSCC, page 424-425. IEEE, (2013)